NCP5210 |
RFQ for NCP5210 Required Field |
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| Technical/Catalog Information | NCP5210MNR2 |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Package / Case | 20-DFN |
| Packaging | Tape & Reel (TR) |
| Type | * |
| Voltage - Input | 4.5 ~ 13.2 V |
| Voltage - Output | 5V, 12V |
| Number of Outputs | 3 |
| Applications | Controller, DDR |
| Operating Temperature | 0°C ~ 70°C |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | NCP5210MNR2 NCP5210MNR2 |
| Product | Manufacturers | Pack | D/C |
| NCP5210 | - | QFN | 04+ |
The NCP5210, 3−In−1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controller for driving four external NFETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current.
Protective features include, soft−start circuitry, under−voltage monitoring of 5VDUAL, and BOOT voltage, and thermal shutdown. The IC is packaged in QFN−20.
Features |
| • Incorporates Synchronous PWM Buck Controllers for VDDQ and VMCH• Integrated Power FETs with VTT Regulator Source/Sink up to 1.8 A• All External Power MOSFETs are N−channel• Adjustable VDDQ and VMCH by External Dividers• VTT Tracks at Half the Reference Voltage• Fixed Switching Frequency of 250 kHz for VDDQ and VMCH• Doubled Switching Frequency (500 kHz) for VDDQ Controller in Standby Mode to Optimize Inductor Current Ripple and Efficiency• Soft−start Protection for all Controllers• Under−Voltage Monitor of Supply Voltages• Over−Current Protections for DDQ and VTT Regulators• Fully Complies with ACPI Power Sequencing Specifications• Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion• Thermal Shutdown• 20−Lead 5x6 QFN Package |
| Rating | Symbol | Value | Unit |
| Power Supply Voltage (Pin 16) to AGND (Pin 7) | 5VDUAL | −0.3, 6.0 | |
| Gate Drive Voltage (Pin 12, 13, 17−19) to AGND (PIN 7) | VCC, Vg | −0.3, 14 | V |
| Input / Output Pins to AGND (Pin 7) Pin 1−6, 8−11, 14−16, 20 |
VIO | −0.3, 6.0 | V |
| Thermal Characteristics QFN−20 Plastic Package Thermal Resistance Junction to Air |
RJA | 35(TBD) | V |
| Operating Junction Temperature Range | TJ | 0 to + 150 | °C/W |
| Operating Ambient Temperature Range | TA | 0 to + 70 | °C |
| Storage Temperature Range | Tstg | − 55 to +150 | °C |
| Moisture Sensitivity Level | MSL | 2 | °C |
1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22A114. Machine Model (MM) 200 V per JEDEC standard: JESD22A115.
2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
